{"id":26724,"date":"2023-08-03T00:15:13","date_gmt":"2023-08-03T00:15:13","guid":{"rendered":"https:\/\/training.linuxfoundation.org\/?p=26724"},"modified":"2025-04-15T13:29:20","modified_gmt":"2025-04-15T13:29:20","slug":"just-launched-computer-architecture-with-an-industrial-risc-v-core-rvfpga-lfd119x","status":"publish","type":"post","link":"https:\/\/training.linuxfoundation.org\/ja\/blog\/just-launched-computer-architecture-with-an-industrial-risc-v-core-rvfpga-lfd119x\/","title":{"rendered":"Just Launched: Computer Architecture with an Industrial RISC-V Core [RVfpga] (LFD119x)"},"content":{"rendered":"<h3 style=\"text-align: center;\"><i><span style=\"font-weight: 400;\"><a href=\"https:\/\/training.linuxfoundation.org\/training\/computer-architecture-with-an-industrial-riscv-core-rvfpga-lfd119x\/\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-38076\" src=\"https:\/\/training.linuxfoundation.org\/wp-content\/uploads\/2025\/04\/LFD119x_sg-300x157.png\" alt=\"Computer Architecture with an Industrial RISC-V Core [RVfpga] (LFD119x) social graphic\" width=\"500\" height=\"262\" srcset=\"https:\/\/training.linuxfoundation.org\/wp-content\/uploads\/2025\/04\/LFD119x_sg-300x157.png 300w, https:\/\/training.linuxfoundation.org\/wp-content\/uploads\/2025\/04\/LFD119x_sg-1024x536.png 1024w, https:\/\/training.linuxfoundation.org\/wp-content\/uploads\/2025\/04\/LFD119x_sg-768x402.png 768w, https:\/\/training.linuxfoundation.org\/wp-content\/uploads\/2025\/04\/LFD119x_sg-18x9.png 18w, https:\/\/training.linuxfoundation.org\/wp-content\/uploads\/2025\/04\/LFD119x_sg.png 1200w\" sizes=\"auto, (max-width: 500px) 100vw, 500px\" \/><\/a><strong>Get a Practical Introduction to Using RISC-V Computer Architecture Based on System-on-Chip<\/strong><\/span><\/i><\/h3>\n<p><a href=\"https:\/\/training.linuxfoundation.org\/\" target=\"_blank\" rel=\"noopener\"><span style=\"font-weight: 400;\">Linux Foundation Training &amp; Certification<\/span><\/a><span style=\"font-weight: 400;\"> today launched the free, edX hosted course: <\/span><a href=\"https:\/\/www.edx.org\/course\/computer-architecture-with-an-industrial-risc-v-core?utm_medium=partner-marketing&amp;utm_source=affiliate&amp;utm_campaign=lftraining&amp;utm_content=landingpage-lfd119x?utm_medium=partner-marketing&amp;utm_source=press&amp;utm_campaign=lftraining&amp;utm_content=blog-lld199x\" target=\"_blank\" rel=\"noopener\"><span style=\"font-weight: 400;\">Computer Architecture with an Industrial RISC-V Core [RVfpga] (LFD119x)<\/span><\/a><span style=\"font-weight: 400;\">. The course is designed for university computer science students, electrical and computer engineers and other technical students and professionals who would like to learn about \u2013 and experiment with \u2013 RISC-V.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">The course provides hands-on experience with RISC-V computer architecture and teaches how to develop and compile C and RISC-V assembly code for the RVfpga SoC. Additionally, participants will learn how to configure the microarchitecture of the SweRV EH1 Core and test its different features using performance counters and industry-standard benchmarks. Finally, the course provides step-by-step instructions on how to execute programs on the Nexys A7 board or by using simulate programs such as:\u00a0<\/span><\/p>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RVfpga-Whisper instruction set simulator (ISS)<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Verilator-based RVfpga-ViDBo<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RVfpga-Pipeline<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RVfpga-Trace<\/span><\/li>\n<\/ul>\n<p><span style=\"font-weight: 400;\">\u201cRISC-V is making fast inroads worldwide,\u201d said Clyde Seepersad, SVP, General Manager, Training &amp; Certification, Linux Foundation. \u201cLearning how to use RISC-V to improve security, power consumption and performance of processors will enable people to help shape the future of computer architecture and ensure long-term career growth.\u201d<\/span><\/p>\n<p><span style=\"font-weight: 400;\">The free, self-paced, online course includes 20 to 40 hours of material and covers:<\/span><\/p>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">C Programming with the RVfpga SoC<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RISC-V Assembly Programming with the RVfpga SoC<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RISC-V Function Calls<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Mixing C and Assembly Functions in a Program<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Peripherals and Input\/Output<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">I\/O: 7-Segment Displays<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">I\/O: Timers<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Interrupts<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RISC-V VeeR Core<\/span><\/li>\n<\/ul>\n<p><span style=\"font-weight: 400;\">It is recommended that participants enrolling in this course have a fundamental understanding of:<\/span><\/p>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Digital logic design<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">High-level programming (such as C programming)<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Assembly programming<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">RISC-V instruction set architecture<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Processor microarchitecture<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Memory and input\/output systems<\/span><\/li>\n<\/ul>\n<p><span style=\"font-weight: 400;\">Interested participants are invited to <\/span><a href=\"https:\/\/www.edx.org\/course\/computer-architecture-with-an-industrial-risc-v-core?utm_medium=partner-marketing&amp;utm_source=affiliate&amp;utm_campaign=lftraining&amp;utm_content=landingpage-lfd119x?utm_medium=partner-marketing&amp;utm_source=press&amp;utm_campaign=lftraining&amp;utm_content=blog-lld199x\" target=\"_blank\" rel=\"noopener\"><span style=\"font-weight: 400;\">enroll<\/span><\/a><span style=\"font-weight: 400;\"> for free today. A verified track to earn a certificate of completion is also available.\u00a0<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u30b7\u30b9\u30c6\u30e0\u30aa\u30f3\u30c1\u30c3\u30d7 Linux \u57fa\u76e4\u306b\u57fa\u3065\u304f RISC-V \u30b3\u30f3\u30d4\u30e5\u30fc\u30bf \u30a2\u30fc\u30ad\u30c6\u30af\u30c1\u30e3\u306e\u4f7f\u7528\u306b\u95a2\u3059\u308b\u5b9f\u8df5\u7684\u306a\u5165\u9580\u3092\u53d6\u5f97\u3059\u308b Linux Foundation \u30c8\u30ec\u30fc\u30cb\u30f3\u30b0\u3068\u8a8d\u5b9a\u306f\u672c\u65e5\u3001\u7121\u6599\u306e edX \u30db\u30b9\u30c8 \u30b3\u30fc\u30b9\u3092\u958b\u59cb\u3057\u307e\u3057\u305f: \u7523\u696d\u7528 RISC-V \u3092\u4f7f\u7528\u3057\u305f\u30b3\u30f3\u30d4\u30e5\u30fc\u30bf \u30a2\u30fc\u30ad\u30c6\u30af\u30c1\u30e3\u2026<\/p>","protected":false},"author":143,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"content-type":"","footnotes":""},"categories":[78],"tags":[],"class_list":["post-26724","post","type-post","status-publish","format-standard","category-announcements"],"acf":[],"_links":{"self":[{"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/posts\/26724","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/users\/143"}],"replies":[{"embeddable":true,"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/comments?post=26724"}],"version-history":[{"count":6,"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/posts\/26724\/revisions"}],"predecessor-version":[{"id":38078,"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/posts\/26724\/revisions\/38078"}],"wp:attachment":[{"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/media?parent=26724"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/categories?post=26724"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/training.linuxfoundation.org\/ja\/wp-json\/wp\/v2\/tags?post=26724"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}