Training > Embedded > Building a RISC-V CPU Core (LFD111x)
Training Course

Building a RISC-V CPU Core (LFD111x)

Create a RISC-V CPU with modern open source circuit design tools, methodologies, and microarchitecture, all from your browser.

Who Is It For

This course is designed for anyone with a technical inclination who is interested in learning more about hardware. Whether you are new to digital logic or are a seasoned veteran, students will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required.
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What You’ll Learn

This is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.
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What It Prepares You For

This course is a hands-on experience with RISC-V and modern circuit design tools. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).
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Course Outline
Welcome!
Chapter 1. Learning Platform
Chapter 2. Digital Logic
Chapter 3. The Role of RISC-V
Chapter 4. RISC-V-Subset CPU
Chapter 5. Completing Your RISC-V CPU
Final Exam (verified track only)

Prerequisites
Anyone with a technical inclination can successfully complete the workshop. No prior knowledge of digital logic design is required.
Reviews
Feb 2022
I liked the ease of starting it - everything was available online, including design software. There was no need to buy, rent or install anything, nor to have any test hardware at hand.
Jan 2022
I liked learning the RISC-V ISA and the TLV, which is way less verbose than other languages, such as VHDL.
Oct 2021
Makerchip simulation was great for testing. The VIZ-Tab is a great help!
Sep 2021
I liked the lessons that got the CPU to stand up fast so we could see the underlying structure, and the amazingly useful visualization.
Sep 2021
I enjoyed the sense of accomplishment as I went through and completed the "hands on" simulation of RISC-V core.