Training > Embedded > Building a RISC-V CPU Core (LFD111x)
Training Course

Building a RISC-V CPU Core (LFD111x)

Create a RISC-V CPU with modern open source circuit design tools, methodologies, and microarchitecture, all from your browser.

Course Rating
4.4/5 Stars
Who Is It For

This course is designed for anyone with a technical inclination who is interested in learning more about hardware. Whether you are new to digital logic or are a seasoned veteran, students will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required.
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What You’ll Learn

This is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.
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What It Prepares You For

This course is a hands-on experience with RISC-V and modern circuit design tools. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).
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Course Outline
Chapter 1. Learning Platform
Chapter 2. Digital Logic
Chapter 3. The Role of RISC-V
Chapter 4. RISC-V-Subset CPU
Chapter 5. Completing Your RISC-V CPU
Final Exam (verified track only)

Anyone with a technical inclination can successfully complete the workshop. No prior knowledge of digital logic design is required.
Dec 2022
What I liked best about this course was the incredible progression that a person can have when doing this course. If you put in the time, you will surely be able to complete the course.
Nov 2022
Able to actually implement a RISC-V CPU core, as stated in the course objectives, yielding a great sense of accomplishment!
Nov 2022
I got a good understanding of what must be done in order to decode instructions of an ISA.
Sep 2022
The assignments were helpful in consolidating the key concepts.
Sep 2022
The content was explained very clearly and effectively, with a hands-on approach.
Sep 2022
Quick introduction to RISC-V CPU and TL-Verilog without needing to set up any software to use it. Everything was available online through EdX and Makerchip.