Training > Embedded > Building a RISC-V CPU Core (LFD111x)
Training Course

Building a RISC-V CPU Core (LFD111x)

Create a RISC-V CPU with modern open source circuit design tools, methodologies, and microarchitecture, all from your browser.

Who Is It For

This course is designed for anyone with a technical inclination who is interested in learning more about hardware. Whether you are new to digital logic or are a seasoned veteran, students will take away new skills that can be applied immediately. No prior knowledge of digital logic design is required.
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What You’ll Learn

This is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip online integrated development environment (IDE), you will implement everything from logic gates to a simple, but complete, RISC-V CPU core. You will be amazed by what you can do using freely-available online tools for open source development. You will familiarize yourself with a number of emerging technologies supporting an open-source hardware ecosystem, including RISC-V, Transaction-Level Verilog, and the online Makerchip IDE.
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What It Prepares You For

This course is a hands-on experience with RISC-V and modern circuit design tools. You will walk away with fundamental skills for a career in logic design, and you will position yourself on the forefront by learning to use the emerging Transaction-Level Verilog language extension (even if you don’t already know Verilog).
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Course Outline
Chapter 1. Learning Platform
Chapter 2. Digital Logic
Chapter 3. The Role of RISC-V
Chapter 4. RISC-V-Subset CPU
Chapter 5. Completing Your RISC-V CPU
Final Exam (verified track only)

Anyone with a technical inclination can successfully complete the workshop. No prior knowledge of digital logic design is required.
Aug 2023
The hands on implementation possible with Makerchip IDE is fantastic, and allows us to quickly go through the implementation.
Jul 2023
I liked being able to run everything for free, with no setup. Extremely impressive!
Jun 2023
I really liked learning about the basics of TL-Verilog. I was planning on learning Verilog, so this introduction was really appreciated, thank you!
Jun 2023
Web IDE is very nice to experiment with, the concepts and visualizations were really helpful towards quickly understanding what to do.
Apr 2023
Really a great course, rather than just teaching concepts, it also encourages students to build the whole system hands-on. The step-by-step guide is really helpful and detailed. Many thanks again, for preparing this fruitful and meaningful journey to all those who are interested in RISC, really a great job.